The present invention relates generally to integrated circuit testing and, more particularly, to a method and apparatus for facilitating the random pattern testing of logic structures.
Integrated circuits (ICs) are tested to ensure that the component is defect-free after being manufactured and/or remains in proper working condition during use. The testing of the IC may be accomplished by applying a test pattern to stimulate the inputs of a circuit and monitoring the output response to detect the occurrence of faults. These test patterns may be applied to the circuit using an external testing device. Alternatively, given the practical reality of limited I/O pin availability and capability, as well as the tester memory needed to store the test patterns, the pattern generator may be a built-in, self test (BIST) structure comprising part of the internal circuitry in the IC which generates the test patterns.
Although it is desirable when testing the logic circuit to use deterministic testing by checking the circuit output response to all 2n possible input permutations, this approach becomes impractical as the number of input variables n and the size of the pattern set increases. Thus, a related technique, referred to as pseudo-random testing, is employed when the number of input variables is so large that it becomes impractical to use an exhaustive testing approach. Pseudo-random testing is an alternative technique that generates test patterns in a random fashion from the 2n possible patterns. In this approach, fewer than all of the 2n patterns are tested. Because of the relatively low hardware overhead and the simplicity of test pattern generation, pseudo-random testing is a preferred technique for BIST. Practical circuits, however, often contain random pattern resistant faults which result in unacceptable low fault coverages and low circuit excitation for a reasonable test length.
Test patterns are typically graded against a fault model (e.g., the stuck-at-fault model). With pseudo-random data, certain random resistant structures are difficult to test. One example of such a xe2x80x9crandom pattern resistantxe2x80x9d logic circuit is a compare circuit that compares the contents of a first register to the contents of a second register. Because the sizes of the registers to be compared can be several bits in length (e.g., 24 bits or even 80 bits or more), it is virtually assured from a statistical standpoint that the random bits generated and loaded into the first register will not exactly match the random bits generated and loaded into the second register. Thus, the compare circuit will almost always be tested in a mismatch condition with a conventional scan chain-based BIST design, even though a test of a match condition is equally (if not more) important. In addition, a xe2x80x9cnear matchxe2x80x9d condition (e.g., where only 1 of 24 bits is mismatched) is also desired test condition. Again, however, the statistical probabilities associated with achieving such a randomly generated data type make random pattern testing of this nature problematic at best. Because compare logic is often found in the most critical of timing paths in IC designs, the quality testing of such logic structures (so as to enable the detection of small delay defects) is a significant concern.
Since no single fault model represents all possible types of defects, a variety of testing techniques are typically employed to test a device. Such techniques may target specific fault models or may exercise the circuit in other ways to detect defects or faulty circuit behavior. Exercising the functional use of a chip is another method that may be used to test a device. However, this method can be very costly to implement, especially at lower packaging levels of a device. For example, during a wafer test, the functional exercising of logic can be either cost prohibitive or physically impossible altogether.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for preparing a logic structure for random pattern testing. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to the second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.
In a preferred embodiment, the first and second registers contain an equal number of data storage elements therein. In addition, a bitflip logic mechanism is configured within the parallel data path, the bitflip logic mechanism capable of inverting one or more data bits passing through the parallel data path. Thus, when the parallel data path is selected as the source path of input data to the second register and the bitflip logic mechanism is activated, the data loaded into the second register may be statistically mismatched from the data loaded into the first register by one bit or more.
Preferably, weight logic is used to control the frequency of occurrences in which the bitflip logic mechanism is caused to invert the data bits passing through the parallel data path. The weight logic further includes a multiple-input AND gate, with each of the multiple inputs being coupled to independent, random bit generating devices. Finally, the bitflip logic mechanism further comprises an exclusive OR (XOR) gate, the XOR gate having the output of the multiple-input AND gate as a first input thereto, and a corresponding data bit in the parallel data path as a second input thereto.